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HV6008 32-Channel 40V Liquid Crystal Display Row Driver
Ordering Information
Package Options 44-Lead Quad Plastic Chip Carrier HV6008PJ 44-Lead Quad Plastic Gullwing HV6008PG
HV6008
Features
Symmetrical 40V output swing Active return to GND 15mA peak source/sink/GND current per channel +5V control logic Special shift register with clear Phase shift control Output enable Data out enable 1MHz shift register Surface mount package available
Absolute Maximum Rati te Ratings
Supply voltage, VDD11 oltage, 1 Supply voltage, ly VDD21 Supply voltage,
bs
VPP1,2 VNN1,2 dissipation3
O
age, Supply voltage, Logic input Ground levels1 els currrent2 Continuous total power Operating temperature range Storage temperature range
03/28/07
VDD1 - 0.3V to VDD2 + 0.3V 700mA 1W -40C to +85C -65C to +150C
Notes: 1. All voltages are referenced to GND. 2. Duty cycle is limited by the total power dissipated in the package. 3. For operation above 25C ambient derate linearly to 85C at 16.7mW/C.
Supertex Inc. does not recommend the use of its products in life support applications and will not knowingly sell its products for use in such applications unless it receives an adequate "products liability indemnification insurance agreement." Supertex does not assume responsibility for use of devices described and limits its liability to the replacement of devices determined to be defective due to workmanship. No responsibility is assumed for possible omissions or inaccuracies. Circuitry and specifications are subject to change without notice. For the latest product specifications, refer to the Supertex website: http://www.supertex.com. For complete liability information on all Supertex products, refer to the most current databook or to the Legal/Disclaimer page on the Supertex website.
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-6V +6V +42V -42V 1
et e
General Description ral
Not recommended for new designs. commended nded ne designs esigns
Device
The HV60 is a 32-channel liquid cr e 32-channe quid crystal display driver with 3-state DMOS outputs. Each output c be set to +40V, -40V, or GND. can D A symmetric waveform can be applied to a capacitive load using the phase shift feature of the HV60.
The HV60 consists of a 32-bit shift register with Clear, Enable, and hase log Phase Shift logic, and 32 high voltage output buffers. With the Enable pin held low, all outputs are placed in the return to zero (GND state. (GND) state When Enable is high, each output reflects the data in its shift register bit. All outputs with a logic "0" in their shift registe register will be in the return to zero state. Outputs with a logic "1" th in their shift register will reflect the state of the phase shift pin. T These outputs will be switched to VPP when phase shift is high and VNN when phase shift is logic "0". Additional functions provided are Shift Register Clear and Data Out. All bits of the shift register are changed to logic "0" when Clear is pulled low. With Clear at a logic "1", normal shift register operation proceeds. The data output reflects the status of the 32nd shift register stage.
HV6008
Electrical Characteristics (over recommended operating conditions unless noted)
DC Characteristics
Symbol IDD1,2 VIH VIL VOH VOL IIH IIL IPP INN VOH VCL VOL ZOH ZCL ZOL IO Parameter VDD supply current Logic input high Logic input low Logic output high Logic output low High-level logic input current Low-level logic input current High voltage supply current High voltage supply current Output voltage high Output voltage clamp Output voltage low Output switch impedence high Output switch impedance clamp Output switch impedance low DC output current Output H or L Data out H or L 1000 500 700 5 150 mA A VPP, VNN = 40 IO = 15mA 1 output only +39 -20 +20 -39 VDD1 VDD2 +2 VDD1 +2 -2 +3 -50 +1 -1 Min Typ Max 500 VDD2 -2 Units A V V V V A A mA mA V mV V Conditions VI = 4V, VDD1 = -6V VI = 4V, VDD2 = +6V VDD1 = -4.5V, VDD2 = +4.5V VDD1 = -4.5V VDD2 = +4.5V IOH = -15A IOL = 250A VI = VDD, VDD1,2 = max VI = 0V, VDD1,2 = max Static, no load Static, no load VPP, VNN = 40 No load
AC Characteristics
Symbol tWH tWL tSU tH Parameter Width of high data pulse Width of low data pulse Data set-up time before clock falls Data hold time after clock falls Phase shift duty cycle Min 500 500 25 10 50 Typ Max Units ns ns ns ns % Conditions
Recommended Operating Conditions
Symbol VDD1 VDD2 VPP VNN VIH VIL IO Pk. TA fDIN fPS Logic supply voltage Logic supply voltage High voltage supply High voltage supply High-level input voltage Low-level input voltage Peak output current (any state) Operating free-air temperature Input data rate Phase shift rate -40 Parameter Min -4 +4 +10 -10 +2V -2V Typ Max -6 +6 +40 -40 VDD2 VDD1 80 +70 1 20 Units V V V V V V mA C MHz KHz
Note: Power-up sequence should be the following: 1. Connect ground. 2. Apply VDD. Power-down sequence should be the reverse of the above.
3. 4.
Set all inputs (Data, CLK, Enable, etc.) to a known state. Apply VPP and VNN.
2
HV6008
Switching Waveform
+ 5V Clock - 5V + 5V Phase Shift - 5V + 5V SR #1 - 5V + 5V SR #2 - 5V + 5V SR #3 - 5V VPP
OUT #1
0V
VNN VPP
OUT #2
0V
VNN VPP
OUT #3
0V
VNN
3
HV6008
Functional Block Diagram
Phase Shifter Enable Data IN T3 HVOUT1 VPP
T1
T2
T4 Clock VNN Clear 32 Bit Shift Register T3 HVOUT32
VPP
T1
T2
T4 Data OUT VNN
Function Table
Inputs Function CLR Reg All output GND Load S/R Data In X X H or L CLK X X
Outputs Enable X L L Phase Shift X X X X * Shift Reg 1 2...32 ALL L *...* HV Outputs 1 2...32 ALL GND ALL GND ALL GND GND GND...GND VPP VNN VPP...VPP VNN...VNN Data Out L * * * * *
CLR H X L
H or L *...* L H H L...L H...H H...H
Output State
X
H or L
L
H
H L
Notes: X = Irrelevant * = Dependent on previous stage's state before the last CLK = High to low transition H = High level L = Low level
4
HV6008
Pin Configurations
44-Pin J-Lead Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 Function HVOUT 16 HVOUT 15 HVOUT 14 HVOUT 13 HVOUT 12 HVOUT 11 HVOUT 10 VPP HVOUT 9 HVOUT 8 HVOUT 7 HVOUT 6 HVOUT 5 HVOUT 4 HVOUT 3 HVOUT 2 HVOUT 1 Data In GND Phase Shift Clock Clear Pin 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 Function VDD 1 Enable VDD 2 GND Data Out HVOUT 32 HVOUT 31 HVOU 30 HVOUT 29 HVOUT 28 HVOUT 27 HVOUT 26 HVOUT 25 HVOUT 24 VNN HVOUT 23 HVOUT 22 HVOUT 21 HVOUT 20 HVOUT 19 HVOUT 18 HVOUT 17
Package Outlines
39 38 37 36 35 34 33 32 31 30 29 40 41 42 43 44 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 28 27 26 25 24 23 22 21 20 19 18
top view
44-pin J Lead Package
44-Pin Quad Palstic Package Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 Function HVOUT 21 HVOUT 20 HVOUT 19 HVOUT 18 HVOUT 17 HVOUT 16 HVOUT 15 HVOUT 14 HVOUT 13 HVOUT 12 HVOUT 11 HVOUT 10 VPP HVOUT 9 HVOUT 8 HVOUT 7 HVOUT 6 HVOUT 5 HVOUT 4 HVOUT 3 HVOUT 2 HVOUT 1 Pin 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 Function Data In GND Phase Shift Clock Clear VDD1 Enable VDD2 GND Data Out HVOUT 32 HVOUT 31 HVOUT 30 HVOUT 29 HVOUT 28 HVOUT 27 HVOUT 26 HVOUT 25 HVOUT 24 VNN HVOUT 23 HVOUT 22
44 43 42 41 40 39 38 37 36 35 34 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 33 32 31 30 29 28 27 26 25 24 23
top view 44-pin Quad Plastic Gullwing Package
03/28/07
(c)2002 Supertex Inc. All rights reserved. Unauthorized use or reproduction prohibited.
5
1235 Bordeaux Drive, Sunnyvale, CA 94089 TEL: (408) 744-0100 * FAX: (408) 222-4895 www.supertex.com
Package Outline 44-Lead PQFP Package Outline (PG)
10x10mm body, 2.45mm height (max.), 0.80mm pitch
D D1
E
E1 Note 1 (Index Area D1/4 x E1/4) L2 48 1 b e L L1 Seating Plane Gauge Plane
Top View
View B A A2 Seating Plane A1
View B
Side View
Note 1: A Pin 1 identifier must be located in the index area indicated. The Pin 1 identifier may be either a mold, or an embedded metal or marked feature.
Symbol MIN Dimension (mm) NOM MAX
A 2.45
A1 0.25 -
A2 1.95 2.00 2.10
b 0.30 0.45
D 13.65 13.90 14.15
D1 9.80 10.00 10.20
E 13.65 13.90 14.15
E1 9.80 10.00 10.20
e 0.80 BSC
L 0.73 0.88 1.03
L1 1.95 REF
L2 0.25 BSC
3.5O 7
O
1 5O 16O
JEDEC Registration M0-112, Variation AA-2, Issue B, Sep.1995. Drawings not to scale.
Doc. #: DSPD-44PQFPPG A082707
Package Outline 44-Lead PLCC Package Outline (PJ)
.653x.653in body, .180in height (max.), .050in pitch
.048/.042 x 45O 6 D D1 1 44 .056/.042 x 45O
40
.150 MAX
Note 1 (Index Area) .075 MAX E1 E
Note 2 (3 places)
0.20max 3 Places
Top View
View B
Side View
b1 A A2 e A1 Base Plane Seating Plane .020 MIN
b
Side View
View B
Note: 1. A Pin 1 identifier must be located in the index area indicated.The Pin 1 identifier may be either a mold, or an embedded metal or marked feature. 2. Exact shape of this feature is optional.
Symbol MIN Dimension (inches) NOM MAX
A .165 .172 .180
A1 .090 .105 .120
A2 .062 .083
b .013 .021
b1 .026 .036
D .685 .690 .695
D1 .650 .653 .656
E .685 .690 .695
E1 .650 .653 .656
e .050 BSC
JEDEC Registration MS-018, Variation AC, Issue A, June, 1993. Drawings are not to scale.
Doc. #: DSPD-44PLCCPJ B051607

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